Standard cell application-specific integrated circuits (ASICs) provide a number of significant advantages over other types of integrated circuits, including more manageable die size, lower piece-part cost, higher performance, and more reliable design flow. The standard cell approach is generally considered preferable to other competing approaches such as custom design and programmable logic. As a result, most existing integrated circuit computer-aided design (CAD) tools, such as place and route tools, are configured for operation with the standard cell approach. Examples of standard cell CAD tools known in the art include the Apollo toolset commercially available from Avanti, and the Silicon Ensemble and First Encounter toolsets commercially available from Cadence Design Systems. In general, CAD tools designed for programmable logic are often incompatible with standard cell tools and may require specially trained experts.
One potential problem associated with the standard cell approach is that non-recurring expense (NRE) and process cycle time for development of a given design may still be unduly high. The principal components of the NRE are the cost of a new lot start and the cost of a new mask set as required to implement changes in a standard cell design. As the transistor technology shrinks in size, the lot start and mask set costs can increase considerably. With regard to process cycle time, ASICs typically undergo several design iterations before qualifying for full production. Reaching production with pure standard cell technology can thus be costly and time consuming at a time when market forces are squeezing costs and shortening development cycles.
A number of techniques have been developed in an attempt to alleviate the above-noted problem of the standard cell approach.
One such technique involves the use of so-called multi-chip shuttles to amortize the lot start and mask set costs over several chips. Basically, a prototype lot is ordered for model production only where there may be four to six individual chips placed on the same wafer and reticle. The drawbacks of this technique include a limited die size for each constituent chip, difficulty in timing and coordination of mask order and other functions across four to six chip projects, and potential saw-apart and packaging problems.
Another known technique involves the embedding of spare standard cell gates in a chip netlist to be used at a later time for design changes. However, these spare gates are generally hand-instantiated into the netlist by the customer, the level of design change supported is extremely limited, and wiring the change into the design can be difficult due to poor cell placement.
A third technique involves embedding programmable logic within a standard cell ASIC. However, as mentioned previously, programmable logic generally requires specialized CAD tools, and thus can create tool interface problems when used in a standard cell ASIC. For example, the use of a gate array place and route tool for a standard cell ASIC will generally require conversion of standard cell tool infrastructure over to the gate array tool and corresponding re-training of standard cell tool users, thereby imposing a high development cost burden on what are typically only a few candidate applications. In addition, the use of programmable logic can create difficult “floor plan” issues. Other drawbacks include the fact that programmable gate array density is typically only half to less than half the density of standard cell, which affects die size and thus piece part cost, and can also impact performance.
Another significant problem associated with the standard cell integrated circuit design approach and other similar techniques is that the use of such techniques can lead to undesirable “antenna errors” in the resulting design. These antenna errors are typically created as a result of place and route operations in the integrated circuit design process. An antenna node refers generally to an electrical node of the integrated circuit, and typically comprises all conducting structures coupled thereto and physically existing at a given processing level of the integrated circuit. An antenna error can result, by way of example and not limitation, when a given antenna node exhibits an excessively large ratio of exposed metal to active gate area. More specifically, the active gate area may be defined in a given application as the total area common to certain active gate materials, such as the total area common to a first polysilicon (Poly 1) layer and a thin gate oxide (TOX). When the ratio of the exposed metal to the active gate area becomes too large, electrostatic charges created on the metal during processing can become large enough to break down the attached gate oxide, thereby destroying the circuit.
In accordance with conventional practice, antenna errors are typically repaired using one of two different approaches. The first approach is to connect each of the antenna nodes that is associated with an antenna error condition to a standard cell diode, where the standard cell diode is added to the design after completion of a place and route process. For example, an N+/Ptub standard cell diode may be connected to the antenna node. However, standard cell diodes added subsequent to the place and route process generally cannot be moved or removed once the ordering of base levels is established. In other words, these standard cell diodes are fixed and cannot be modified as needed unless all mask levels are changed, which is an unduly expensive and time-consuming process. A possible variant of this first approach is to add a diode to every standard cell input, but this is very area inefficient.
The second approach mentioned above is to repair a given antenna error by breaking the metal as close as possible to the gate and re-routing or “jogging” the metal to an upper metal layer. However, automated techniques for implementing this approach generally do not fix all of the antenna errors and in a given application can leave hundreds of unresolved errors.
It is therefore apparent that a need exists for improved techniques for correcting antenna errors in an integrated circuit design, preferably in a manner that is programmable but also fully compatible with standard cell CAD tools.